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AS1524/as1525 150ksps, 12-bit, 1-channel pseudo/true-differential and 2-channel single-ended adcs www.austriamicrosystems.com revision 1.02 1 - 22 datasheet 1 general description the AS1524/as1525 are low-power, 12-bit analog-to- digital converters (adcs) de signed to operate with a sin- gle +2.7v to +5.25v supply. excellent dynamic perfor- mance, low power consumpt ion, and simplicity make these devices perfect for portable battery-powered data- acquisition applications. the devices are available as the standard products listed in ta b l e 1 . the devices feature a succe ssive-approximation regis- ter (sar), automatic shutdo wn, fast wakeup (1.4s), and low-power consumption at the maximum sampling rate of 150ksps. automatic shutdown (0.2a) between conversions results in reduced power consumption (at slower throughput rates). data access are made via an external clock through the spi-/qspi-/microwire-compa tible 3-wire high-speed serial interface. the as1525/AS1524 are available in a 8-pin tdfn (3x3mm) package. figure 1. AS1524/as1525 - block diagram 2 key features single-supply operation: +2.7v to +5.25v automatic shutdown between conversions low power consumption - 350a @ 150ksps - 245a @ 100ksps -24a @ 10ksps - 2.5a @ 1ksps - 200na in automatic shutdown mode true-differential track/hold, 150khz sampling rate software-configurable unipolar/bipolar conversion (AS1524) input common mode range from gnd to v dd 3-wire spi-/qspi-/microwire-compatible serial interface internal conversion clock 8-pin tdfn (3x3mm) package 3 applications the devices are ideal for remote sensors, data-acquisi- tion, data logging devices, lab instruments, or for any other space-limited a/d devices with low power con- sumption and single-supply requirements. table 1. standard products model input type input voltage AS1524 1-channel, pseudo / true-differential 0 to v ref / -v ref /2 to v ref /2 as1525 2-channel, single- ended 0 to v ref AS1524/as1525 control logic input shift register osc track/ hold 6 dout 5 gnd 1 vdd 7 cnvst 8 sclk 4 ref 12-bit sar 2 ain1/ain+ 2 ain2/ain-
www.austriamicrosystems.com revision 1.02 2 - 22 AS1524/as1525 datasheet contents 1 general description ......................................................................................................... .................... 1 2 key features ................................................................................................................ ........................ 1 3 applications ................................................................................................................ .......................... 1 4 pinout ...................................................................................................................... ............................. 3 pin assignment ................................................................................................................ ................................... 3 pin description ................................................................................................................ ..................................... 3 5 absolute maximum ratings .. .................................................................................................. ............. 4 6 electrical characteristics .................................................................................................. .................... 5 timing characteristics ............... .......................................................................................... ................................ 7 7 typical operating characteristics ................ ........................................................................... ............. 8 8 detailed description ........................................................................................................ ................... 11 true differential analog input tra ck/hold ........... .............. .............. .............. ........... ............ .......... .................... 11 selecting ain1 or ain2 (as1525) ...................... ......................................................................... ....................... 11 selecting unipolar or bipolar conversions (AS1524) ... ............. .............. .............. ........... ........... ........... ............12 input bandwidth ................................................................................................................ ..................................13 analog input protection ........................................................................................................ ..............................13 internal clock ................................................................................................................. .....................................13 output data format ............................................................................................................. ...............................13 transfer function .............................................................................................................. ..................................13 9 application information ..................................................................................................... .................. 15 automatic shutdown mode ........................................................................................................ .........................15 external reference ............................................................................................................. ................................15 performing a conversion ........................................................................................................ ............................15 standard interface connections ............................. .................................................................... .........................15 spi and microwire interface ............................... ..................................................................... ....................... 15 qspi interface ................................................................................................................ ................................16 pic16 and ssp module and pic17 interface .............. ........................................................................ ..........17 layout and grounding considerations ............................................................................................ .................. 19 10 package drawings and markings .............................................................................................. ...... 20 11 ordering information ........ ............................................................................................... ................. 21
www.austriamicrosystems.com revision 1.02 3 - 22 AS1524/as1525 datasheet - pinout 4 pinout pin assignment figure 2. pin assignments (top view) pin description table 2. pin description pin number pin name description 1 vdd positive supply voltage. +2.7v to +5.25v. note: bypass with a 0.1f capacitor to gnd. 2ain1/ain+ analog input channel 1 (as1525) or positive analog input (AS1524) 3ain2/ain- analog input channel 2 (as1525) or negative analog input (AS1524) 4gnd ground 5ref external reference voltage input. sets the analog voltage range. note: bypass with a 4.7f capacitor to gnd. 6 cnvst conversion start . a rising edge powers up the device and puts the track/ hold circuitry in track mode. at the falling edge of this pin, the device enters hold mode and begins a conversion. note: this pin also selects the input channel (as1525) or input polarity (AS1524). 7dout serial data output. this pin transitions the falling edge of sclk and goes low at the start of a conversion and delivers the msb at the completion of a conversion. note: this pin goes high impedance once data has been fully clocked out. 8sclk serial clock input. clocks out data at dout with the msb first. AS1524/ as1525 4 gnd 3 ain2/ain- 2 ain1/ain+ 1 v dd 5 ref 7dout 8 sclk 6cnvst
www.austriamicrosystems.com revision 1.02 4 - 22 AS1524/as1525 datasheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 3 may cause permanent damage to the device. these are stress ratings only, and functional operation of the de vice at these or any other cond itions beyond those indicated in electrical character- istics on page 5 is not implied. exposure to absolute maximum ra ting conditions for extended periods may affect device reliability. table 3. absolute maximum ratings parameter min max units comments vdd to gnd -0.3 +6 v cnvst, sclk, dout, ref, ain1/ ain+, ain2/ain- to gnd -0.3 v dd + 0.3 v current into any pin 50 ma continuous power dissipation 1491 mw t amb = +70oc; derate 19.5mw/oc above +70oc operating temperature range -40 +85 oc storage temperature range -60 +150 oc package body temperature +260 oc the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/jedec j-std-020d ?moisture/reflow sensitivity classi fication for no n-hermetic solid state surface mount devices?. the lead finish for pb-free leaded packages is matte tin (100% sn).
www.austriamicrosystems.com revision 1.02 5 - 22 AS1524/as1525 datasheet - electrical characteristics 6 electrical characteristics v dd = +2.7 to +5.25v, v ref = +2.5v, 4.7f capacitor at ref; f sclk = 8mhz (50% duty cycle); ain- = gnd (AS1524) t amb = t min to tmax (unless otherwise specified). typical values at t amb = +25oc. unipolar mode (AS1524). table 4. electrical characteristics symbol parameter condition min typ max unit dc accuracy resolution 12 bits inl relative accuracy 1.0 lsb dnl differential non-lineraity no missing codes over temperature -0.99 +1.0 lsb offset error 1 4 lsb gain error 1 1 4 lsb gain temp coefficient 0.3 ppm/oc offset temp coefficient 0.3 ppm/oc channel-to-channel offset match 0.1 lsb channel-to-channel gain match 0.1 lsb dynamic specifications ? (f in (sinewave) = 10khz, v in = 2.5v p-p , 150ksps, f sclk = 8mhz (50% duty cycle), ain- = gnd (AS1524) sinad signal-to-noise plus distortion 72.5 db thd total harmonic distortion (to the 5th harmonic) -79.5 db sfdr spurious-free dynamic range 84 db full power bandwidth -3db point 20 mhz full linear bandwidth -0.1db point 400 khz conversion rate t conv conversion time exclusive of t acq 3.3 3.7 s t acq track/hold acquisition time 1.4 s aperture delay 30 ns f sclk max serial clock frequency 8 mhz serial clock duty cycle 30 70 % analog input v in range 2 unipolar 0 v ref v bipolar -v ref /2 v ref /2 input leakage current no channel selected or conversion halted 0.01 1 a input capacitance track mode 20 pf hold mode 5 pf external reference input v ref v in range 1.0 v dd + 50mv v i ref input current v ref = +2.5v @ 150ksps 11 25 a v ref = +4.096v @ 150ksps 19 acquisition between conversions 0 +2 +5
www.austriamicrosystems.com revision 1.02 6 - 22 AS1524/as1525 datasheet - electrical characteristics digital inputs/outputs (cnvst, sclk, dout) v il input low voltage 0.3v dd v v ih input high voltage 0.7v dd v i leak input leakage current 0.01 1.0 a c in input capacitance 15 pf v ol output low voltage i sink = 2ma 0.4 v i sink = 4ma 0.8 v oh output high voltage i source = 1.5ma 0.7v dd v tri-state leakage current cnvst = gnd 0.05 5 a tri-state output capacitance cnvst = gnd 15 pf power requirements v dd positive supply voltage 2.7 5.25 v i dd positive su pply current v dd = +3v, f sample = 150ksps 350 425 a v dd = +3v, f sample = 100ksps 245 v dd = +3v, f sample = 10ksps 24 v dd = +3v, f sample = 1ksps 2.5 v dd = +5v, f sample = 150ksps 485 550 v dd = +5v, f sample = 100ksps 330 v dd = +5v, f sample = 10ksps 33 v dd = +5v, f sample = 1ksps 3.7 automatic shutdown mode 0.2 1 psr power supply rejection v dd = +5v 5%, full scale input 0.3 mv v dd = +2.7v to 3.6v, full scale input 0.4 1. offset nulled. 2. the absolute input voltage range for the analog inputs is from gnd to v dd . table 4. electrical characteristics (continued) symbol parameter condition min typ max unit
www.austriamicrosystems.com revision 1.02 7 - 22 AS1524/as1525 datasheet - electrical characteristics timing characteristics v dd = +2.7 to +5.25v, v ref = +2.5v, 4.7f capacitor at ref; f sclk = 8mhz (50% duty cycle); ain- = gnd (AS1524) t amb = t min to tmax (unless otherwise specified). typical values at t amb = +25oc. figure 3. dout enable/disable time load circuits figure 4. detailed serial interface timing diagram table 5. timing characteristics parameter symbol conditions min typ max units sclk pulse width high t ch 38 ns sclk pulse width low t cl 38 ns sclk falling-to-dout transition t dot c load = 30pf (see figure 3 , figure 4 , figure 19 on page 12 , figure 20 on page 12 ) 28 60 ns sclk rising-to-dout 1 disable 1. guaranteed by design and characterisation. t dod c load = 30pf (see figure 3 , figure 4 , figure 19 on page 12 , figure 20 on page 12 ) 100 200 500 ns cnvst falling-to-msb vlid t conv c load = 30pf (see figure 3 , figure 4 , figure 19 on page 12 , figure 20 on page 12 ) 3.3 3.7 s cnvst pulse width tcsw 30 ns c load 6k gnd gnd dout dout high-impedance to v oh , v ol to v oh , and v oh to high-impedance v dd 6k gnd c load dout sclk cnvst t cl t ch t dot t dod t csw high z
www.austriamicrosystems.com revision 1.02 8 - 22 AS1524/as1525 datasheet - typical operating characteristics 7 typical operating characteristics v dd = 5v; v ref = 2.5v, f sclk = 8mhz(50% duty), c ref = 4.7f, t amb = +25oc (unless otherwise specified). figure 5. integral nonlinearity vs. digital output code fi gure 6. differential nonlinea rity vs. digital output code figure 7. supply current vs. supply voltage figure 8. supply current vs. temperature figure 9. supply current vs. temperature, v dd = 3v figure 10. supply current vs. sampling rate -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 1024 2048 3072 4096 digital output code dnl (lsb) . -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 1024 2048 3072 4096 digital output code inl (lsb) . f sample = 150ksps f sample = 150ksps 0 50 100 150 200 250 300 350 400 450 500 -45 -30 -15 0 15 30 45 60 75 90 temperature (c) supply current (a) . 150ksps 100ksps 10ksps 1ksps 0 100 200 300 400 500 600 2.7 3.2 3.7 4.2 4.7 5.2 supply voltage (v) supply current (a) . f sample = 150ksps 0 40 80 120 160 200 240 280 320 360 -45 -30 -15 0 15 30 45 60 75 90 temperature (c) supply current (a) . 150ksps 100ksps 10ksps 1ksps 0.01 0.1 1 10 100 1000 0.01 0.1 1 10 100 1000 sampling rate (ksps) supply current (a) .
www.austriamicrosystems.com revision 1.02 9 - 22 AS1524/as1525 datasheet - typical operating characteristics figure 11. shutdown current vs. supply voltage figure 12. shutdown cu rrent vs. temperature figure 13. offset error vs. supply voltage figure 14. offset error vs. temperature figure 15. gain error vs. supply voltage figure 16. gain error vs. temperature 0 10 20 30 40 50 60 70 80 90 100 -45 -30 -15 0 15 30 45 60 75 90 temperature (c) shutdown current (na) . 0 1 2 3 4 5 6 7 8 9 10 2.73.23.74.24.75.2 supply voltage (v) shutdown current (na) . -2 -1 0 1 2 -45 -30 -15 0 15 30 45 60 75 90 temperature (c) offset error (lsb) . -2 -1 0 1 2 2.7 3.2 3.7 4.2 4.7 5.2 supply voltage (v) offset error (lsb) . -2 -1 0 1 2 -45 -30 -15 0 15 30 45 60 75 90 temperature (c) gain error (lsb) . -2 -1 0 1 2 2.7 3.2 3.7 4.2 4.7 5.2 supply voltage (v) gain error (lsb) .
www.austriamicrosystems.co m revision 1.02 10 - 22 AS1524/as1525 datasheet - typical operating characteristics figure 17. fft @ 10khz -160 -140 -120 -100 -80 -60 -40 -20 0 0 1530456075 input signal frequency (khz) fft (dbc) . f sample = 150ksps n fft = 32768 snr=72.7db thd = -79.3db sfdr = 83.5db
www.austriamicrosystems.co m revision 1.02 11 - 22 AS1524/as1525 datasheet - detailed description 8 detailed description the AS1524/as1525 employ a successive approximation conver sion (sar) technique and integrated track/hold cir- cuitry to convert analog signals into 12-bit digital output. the serial interface provides easy interfacing to microproces- sors. figure 18 shows the simplified internal structure for t he as1525 (2-channels, single ended) and the AS1524 (1-channel, true differential). true differential analog input track/hold the equivalent circuit of figure 18 shows the device input architecture which is composed of track/hold circuitry, input multiplexer, comparator, and switched-capacitor dac. the track/hold circuitry enters its tracking mode on the rising edge of cnvst. the positive input capacitor is connected to ain1 or ain2 (as1525) or ain+ (AS1524). the negative input capacitor is connected to gnd (as1525) or ain- (AS1524). figure 18. equivalent input circuit the track/hold circuitry enters its hold mode on the fallin g edge of cnvst and the difference between the sampled positive and negative input voltages is converted. the time required for the track/hold to acquire an input signal is determined by how quickly its input capacitance is charged. if the input signal?s source impedance is high, the acquisi- tion time lengthens, and cnvst must be held high for a longer period of time. the acquisition time ( tacq) is the maxi- mum time needed for the signal to be acquired, plus the power-up time. tacq is calculated by: t acq = 9 x (r s + r in ) x 20pf + t pwr (eq 1) where: r s is the source impedance of the input signal; r in = 1.5k ; t pwr of 1s is the power-up time of the device. note: tacq is never less than 1.4s and any source impedance below 300. does not signific antly affect the AS1524/ as1525 ac performance. a high-impedance source can be accommodated either by lengthening tacq or by placing a 1f capacitor between the positive and negative analog inputs. selecting ain1 or ain2 (as1525) select one of the as1525 two positive input channels using the cnvst pin (see page 3) . if ain1 is selected (see fig- ure 19) , drive cnvst high to power up the as1525 and place the track/hold circuitry in track mode with ain1 con- nected to the positive input capacitor. hold cnvst high for tacq to fully acquire the signal. drive cnvst low to place the track/hold circuitry in hold mode. the as1525 then performs a conversion and shutdow n automatically. the msb is available at dout after 3.7s. data can then be clocked out using sclk. clock out all 12 bits of data before driving cnvst high for the next conversion. if all 12 bits of dat a are not clocked out before cn vst is driven high, ain2 is selected for the next conversion. ? + comparator hold hold 12-bit capacitive dac track ain2 ain1/ain+ v dd/2 r in- c in+ ref gnd gnd/ain- c in- hold r in+
www.austriamicrosystems.co m revision 1.02 12 - 22 AS1524/as1525 datasheet - detailed description figure 19. single conversion ? ain1 vs. gnd ( as1525), unipolar mode ain+ vs. ain- (AS1524) if ain2 is selected (see figure 20) , drive cnvst high for at least 30ns. next, drive cnvst low for at least 30ns, and then high again. this powers up the as 1525 and places the track/hold circuitry in track mode with ain2 connected to the positive input capacitor. next hold cnvst high for tacq to fully acquire the signal. drive cnvst low to place the track/hold circuitry in hold mode. the as1525 then performs a conversion and shuts down automatically. the msb is available at dout after 3.7s. data can then be clocked out using sclk. note: if all 12 bits of data are not clocked out before cnvst is driven high, ain2 is sele cted for the next conversion. selecting unipolar or bi polar conversions (AS1524) true-differential conversion (with the AS1524 unipo lar and bipolar modes) is selected using pin cnvst (see page 3) . ain+ and ain- are sampled at the falling edge of cnvst. in unipolar mode, ain+ can exc eed ain- by up to vref. the output format is straight binary. in bipolar mode, either input can exceed the other by up to v ref/2 . the output format is two?s complement. in both modes, the input common mode range can go from gnd to v dd . figure 20. single conversion ? ain2 vs. gnd (as1525), bipolar mode ain+ vs. ain- (AS1524) note: in unipolar and bipolar modes, ain+ and ain- must not exceed v dd by more than 50mv or be lower than gnd by more than 50mv. if unipolar mode is selected (see figure 19) , drive cnvst high to power up the AS1524 and place the track/hold cir- cuitry in track mode with ain+ and ain- connec ted to the input capacitors. hold cnvst high for tacq to fully acquire the signal. drive cnvst low to place the track/hold circuitr y in hold mode. the AS1524 then performs a conversion and shutdown automatically. the msb is available at dout after 3.7s. data can then be clocked out using sclk. clock out all 12 bits of data before driving cnvst high for t he next conversion. if all 12 bits of data are not clocked out before cnvst is driven high, bipolar mo de is selected for the next conversion. if bipolar mode is selected (see figure 20) , drive cnvst high for at least 30ns. next, drive cnvst low for at least 30ns and then high again. this places the track/hold circui try in track mode with ain+ and ain- connected to the input capacitors. next hold cnvst high for tacq to fully acquire the signal. drive cnvst lo w to place the track/hold circuitry in hold mode. the AS1524 then performs a conversion and shuts down automatically. the msb is available at dout after 3.7s. data can then be clocked out using sclk. note: if all 12 bits of data are not clocked out before cnvst is driven high, bipolar mode is selected for the next con- version. sclk cnvst sampling instant t conv t acq 1 4 8 12 dout b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b11 msb b0 lsb high z high z dout sclk cnvst b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b11 msb b0 lsb sampling instant t conv t acq 1 4 8 12 high z high z
www.austriamicrosystems.co m revision 1.02 13 - 22 AS1524/as1525 datasheet - detailed description input bandwidth the AS1524/as1525 input tracking circuitry has a 20mhz small signal bandwidth, so it is possible to digitize high- speed transient events and measure periodic signals with bandwidths exceeding the AS1524/as1525 sampling rate by using undersampling techniques. note: to avoid high-frequency signals being aliased into the fr equency band of interest, anti-alias filtering is recom- mended. analog input protection internal protection diodes t hat clamp the analog input to v dd and gnd allow the analog input pins to swing from gnd - 0.3v to v dd + 0.3v without damage. both inputs must not exceed v dd by more than 50mv or be lower than gnd by more than 50mv for accurate conversions. note: if an off-channel analog input voltage exceeds the supply voltages, the input current should be limited to 2ma. internal clock the AS1524/as1525 operate from an internal clock, which is accu rate within 5% of the 4mhz clock rate. this results in a worst-case conversion time of 3.7s. the internal cloc k releases the system microp rocessor from running the sar conversion clock and allows the conversion results to be read back at the processor?s convenience, at any clock rate from 0 to 8mhz. output data format figure 19 on page 12 and figure 20 on page 12 illustrate the conversion timing for the AS1524/as1525. the 12-bit conversion result is output in msb-first format. data on dout transitions on the falling edge of sclk. all 12 bits must be clocked out before cnvst transitions again. for the AS1524, data is straight binary for unipolar mode and two?s complement for bipolar mode. for the as1525, data is always straight binary. transfer function figure 21 on page 13 shows the unipolar transfer function for the AS1524/as1525. figure 22 on page 14 shows the bipolar transfer function for the AS1524. code transitions occur halfway between succe ssive-integer lsb values. figure 21. AS1524/as1525 unipolar transfer function 11...111 11...110 11....101 00...011 00...010 00...001 00...000 output code input voltage (lsb) 0 1 2 3 fs-3/2 lsb fs full-scale transition full scale = v ref zero scale = gnd 1 lsb = v ref /4096
www.austriamicrosystems.co m revision 1.02 14 - 22 AS1524/as1525 datasheet - detailed description figure 22. AS1524 bipolar transfer function 011...111 011...110 000...010 000...001 000...000 111...111 111...110 111...101 100...001 100...000 output code input voltage (lsb) -fs 0 +fs-1 lsb v com v ref /2 v in = ain+ - ain- full scale = v ref /2 -full scale = -v ref /2 zero scale = 0 1 lsb = v ref /4096
www.austriamicrosystems.co m revision 1.02 15 - 22 AS1524/as1525 datasheet - application information 9 application information automatic shutdown mode with cnvst low, the AS1524/as1525 default to automatic shutdown (< 0.2a) mode after power-up and between conversions. after detecting a rising edge of cnvst, the AS1524/as1525 powers up, sets dout low, and enters track mode. after detecting a falling edge of cnvst, the device enters hold mode and begins the conversion. a maximum of 3.7s later, the device completes conversion, enters shutdown, and msb is available at dout. external reference an external reference is required for the AS1524/as1525. use a 4.7f bypass capacitor for best performance. the reference input structure allows a voltage range of +1v to v dd + 50mv. performing a conversion 1. use a general-purpose i/ o line on the cpu to hold cnvst low between conversions. 2. drive cnvst high to acquire ain1(as1525) or unipola r mode (AS1524). to acquire ain2 (as1525) or bipolar mode (AS1524), drive cnvst low and high again. 3. hold cnvst high for 1.4s. 4. drive cnvst low and wait approximately 3.7s for conv ersion to complete. after 3.7s, the msb is available at dout. 5. activate sclk for a minimum of 12 rising clock edges. dout transitions on sclk?s falling edge and is avail- able in msb-first format. observe the sclk to dout va lid timing characteristic. clock data into the p on sclk?s rising edge. standard interface connections the AS1524/as1525 serial interface is fully compatible with spi, qspi, and microwire. if a serial interface is avail- able, establish the processor?s serial interface as a master so that the cpu generates the serial clock for the AS1524/ as1525 and select a clock frequency up to 8mhz. spi and microwire interface when using an spi ( figure 23 ) or microwire interface ( figure 24 ), set cpol = cpha = 0. two 8-bit readings are nec- essary to obtain the entire 12-bit re sult from the AS1524/as1525. dout data transitions on the serial clock?s falling edge and is clocked into the processor on sclk?s rising edge. the first 8-bit data stream co ntains the first 8-bits of dout starting with the msb. the second 8- bit data stream contains the remaini ng four result bits. dout then goes high impedance. figure 23. spi serial interface connections AS1524/ as1525 cpu ssm miso i/o sck 7 dout 6 cnvst 8 sclk
www.austriamicrosystems.co m revision 1.02 16 - 22 AS1524/as1525 datasheet - application information figure 24. microwire serial interface connections figure 25. spi/microwire interface timing diagram (cpol = cpha = 0) qspi interface using the high-speed qspi interface ( figure 26 ) with cpol = 0 and cpha = 0, the AS1524/as1525 support a maxi- mum f sclk of 8mhz. one 12- to 16-bit reads are necessary to obtain the entire 12 -bit result from the AS1524/as1525. dout data transitions on the serial clock?s falling edge an d is clocked into the processor on sclk?s rising edge. the first 12 bits are the data. dout then goes high impedance (see figure 24) . figure 26. qspi serial interface connections AS1524/ as1525 cpu si i/o sk 7 dout 6 cnvst 8 sclk sclk cnvst sampling instant 1 4 8 12 dout b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b11 msb b0 lsb high z 16 1st byte read 2nd byte read AS1524/ as1525 cpu ssm miso csm sck 7 dout 6 cnvst 8 sclk
www.austriamicrosystems.co m revision 1.02 17 - 22 AS1524/as1525 datasheet - application information figure 27. qspi serial interface timing (cpol = cpha = 0) pic16 and ssp module and pic17 interface the AS1524/as1525 are compatible with a pic16/pic17 controllers, using the synchronous serial port (ssp) module to establish spi communication, connect the pic16/pic17 controllers as shown in figure 28 and configure the pic16/ pic17 as system master. this is done by initializing its synchronous serial po rt control re gister (sspcon) and syn- chronous serial port stat us register (sspstat) to the bit patterns shown in table 6 on page 18 and table 7 on page 18 . figure 28. spi interface connections for pic16/pic17 controller in spi mode, the pic16/pic17 processor allow 8 bits of data to be synchronous ly transmitted and received simultane- ously. two consecutive 8-bit readings (see figure 29) are necessary to obtain the enti re 12-bit result from the AS1524/ as1525. dout data transitions on the serial clock?s falling edge and is clocked into the processor on sclk?s rising edge. the first 8-bit data stream contains the first 8 data bits starting with the msb. the second data stream contains the remaining bits, d3 through d0. figure 29. spi interface timing with pic16/pic17 in master mode (c ke = 1. ckp = 0. smp = 0, sspm3:sspm0 = 0001) sclk cnvst sampling instant 1 4 8 12 dout b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b11 msb b0 lsb high z 16 AS1524/ as1525 pic16/ pic17 dout cnvst sclk 7 dout 6 cnvst 8 sclk sclk cnvst sampling instant 1 4 8 12 dout b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b11 msb b0 lsb high z 16 1st byte read 2nd byte read
www.austriamicrosystems.co m revision 1.02 18 - 22 AS1524/as1525 datasheet - application information table 6. sspcon register settings control bit AS1524/as1525 setting synchronous serial port control register (sspcon) wcol bit 7 x write collision detection bit sspov bit 6 x receive overflow detect bit sspen bit 5 1 synchronous serial port enable 0: disables serial port and confi gures these pins as i/o port pins. 1: enables serial port and configures sck, sdo, and sci pins as serial port pins. ckp bit 4 0 clock polarity select bit . ckp = 0 for spi mast er mode selection. sspm3:1 bit 3:1 0 synchronous serial port mode select bit. sets spi master mode and selects fclk = fosc / 16. sspm0 bit 0 1 table 7. sspstat register settings control bit AS1524/as1525 setting synchronous serial status register (sspstat) smp bit 7 0 spi data input sample phase. input data is sampled at the middle of the data output time. cke bit 6 1 spi clock edge select bit. data is transmitted on the rising edge of the serial clock. d/a bit 5 x data address bit pbit 4 x stop bit sbit 3 x start bit r/w bit 2 x read/write bit information ua bit 1 x update address bf bit 0 x buffer full status bit
www.austriamicrosystems.co m revision 1.02 19 - 22 AS1524/as1525 datasheet - application information layout and groundi ng considerations the AS1524/as1525 require proper layout and design procedures for optimum performance. use printed circuit boards; wirewrap boards should not be used. separate analog and digital traces from each other. analog and digital traces should not run parallel to each other (especially clock traces). digital traces should not run beneath the AS1524/as1525. use a single-point analog ground at g nd, separate from the digital ground (see figure 30) . connect all other ana- log grounds and dgnd to this star ground point for further noise reduction. no other digital system ground should be connected to this single-point analog ground. the ground return to the power supply for this ground should be low impedance and as short as possible for noise-free operation. high-frequency noise in the v dd power supply may affect the AS1524/as1525 high-speed comparator. bypass this supply to the single-point analog ground with 0.1f and 4.7f bypass capacitors (see figure 30) . the bypass capacitors should be placed as close to the device as possible for optimum power supply noise-rejection. if the power supply is very noisy, a 10 resistor can be connected as a low-pass filter to attenuate supply noise power components such as the inductor, converter ic, filter capacitors, and output diode should be placed as close together as possible, and their traces should be kept short, direct, and wide. keep the voltage feedback network very close to the device, within 5mm (0.2?) of the pin. keep noisy traces, such as those from the pin lx, away from the voltage feedback network and guarded from them using grounded copper traces. figure 30. recommended ground design AS1524/ as1525 power supplies digital circuitry 0.1f gnd +5 or +3v 1 v dd 4 gnd +5 or +3v +5 or +3v dgnd gnd 5 (optional)
www.austriamicrosystems.co m revision 1.02 20 - 22 AS1524/as1525 datasheet - package drawings and markings 10 package drawings and markings the devices are available in a 8-pin tdfn (3x3mm) package. figure 31. 8-pin tdfn (3x3mm) packagee notes: 1. figure 31 is shown for illustration only. 2. all dimensions are in millimeters; angles in degrees. 3. dimensioning and tolerancing conform to asme y14.5 m-1994 . 4. n is the total number of terminals. 5. the terminal #1 identifier and terminal numbering convention shall conform to jedec 95-1, spp-012 . details of ter- minal #1 identifier are optional, but must be located within t he zone indicated. the terminal #1 identifier may be either a mold or marked feature. 6. dimension b applies to metallized terminal and is me asured between 0.15mm and 0.30mm from the terminal tip. 7. nd refers to the maximum number of terminals on side d. 8. unilateral coplanarity zone applies to the ex posed heat sink slug as well as the terminals symbol min typ max notes a 0.70 0.75 0.80 1, 2 a1 0.00 0.02 0.05 1, 2 a3 0.20 ref 1, 2 l1 0.15 1, 2 l2 0.13 1, 2 aaa0.151, 2 bbb0.101, 2 ccc 0.10 1, 2 ddd0.051, 2 eee0.081, 2 ggg0.101, 2 symbol min typ max notes d bsc 3.00 1, 2 e bsc 3.00 1, 2 d2 1.60 2.50 1, 2 e2 1.35 1.75 1, 2 l 0.30 0.40 0.50 1, 2 0o 14o 1, 2 k0.20 1, 2 b 0.25 0.30 0.35 1, 2, 5 e0.65 n81, 2 nd 4 1, 2, 5 see detail b pin 1 index area (d/2 xe/2) btm view n-1 n b bb ddd d2 d2/2 b (d/2 xe/2) 2x 2x top view aaa c aaa c e pin 1 index area d ccc c a side view (nd-1) x e e 0.08 c a1 a b l even terminal side datum a or b terminal tip e e/2 c a b c e2 e2/2 seating plane a3 k c detail b
www.austriamicrosystems.co m revision 1.02 21 - 22 AS1524/as1525 datasheet - ordering information 11 ordering information the devices are available as the standard products shown in table 8 . note: all products are rohs compliant and pb-free. buy our products or get free samples online at icdirect: http://www.austriamicr osystems.com/icdirect for further information and requests, please contact us mailto:sales@austriamicrosystems.com or find your local distributor at http://www.a ustriamicrosystems.com/distributor table 8. ordering information ordering code description delivery form package AS1524-btdt 150ksps, 12-bit, 1-channel true-differential adc tape & reel 8-pin tdfn (3x3mm) AS1524-btdr 150ksps, 12-bit, 1-channel true-differential adc tray 8-pin tdfn (3x3mm) as1525-btdt 150ksps, 12-bit, 2-channel single-ended adc tape & reel 8-pin tdfn (3x3mm) as1525-btdr 150ksps, 12-bit, 2-channel single-ended adc tray 8-pin tdfn (3x3mm)
www.austriamicrosystems.co m revision 1.02 22 - 22 AS1524/as1525 datasheet copyrights copyright ? 1997-200 9, austriamicrosystems ag, tobelbaderstrasse 30, 8141 unterpremstaet ten, austria-europe. trademarks registered ?. all rights reserved. the mate rial herein may not be reproduced, adapted, merged, translated, stored, or used wit hout the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by t he warranty and patent indemni fication provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freed om of the described devices from patent infringement. austriamicrosystems ag reserves the right to change spec ifications and prices at an y time and without notice. therefore, prior to designing this pro duct into a system, it is necessary to check with austriam icrosystems ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temperature range, unus ual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems ag for each application. for shipments of less than 100 parts the m anufacturing flow might show deviations from the standard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to reci pient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters austriamicrosystems ag tobelbaderstrasse 30 a-8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors a nd representatives, please visit: http://www.austriamicrosystems.com/contact

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